set sdc_version 2.0

set_units -time ps -resistance kOhm -capacitance fF -voltage V -current mA
set_max_fanout 40 [current_design]
set_max_area 0
set_driving_cell -lib_cell in01f80 [get_ports rst_i]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[31]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[30]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[29]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[28]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[27]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[26]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[25]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[24]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[23]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[22]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[21]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[20]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[19]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[18]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[17]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[16]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[15]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[14]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[13]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[12]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[11]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[10]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[9]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[8]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[7]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[6]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[5]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[4]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[3]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[2]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[1]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0s_data_i[0]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[31]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[30]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[29]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[28]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[27]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[26]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[25]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[24]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[23]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[22]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[21]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[20]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[19]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[18]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[17]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[16]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[15]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[14]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[13]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[12]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[11]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[10]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[9]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[8]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[7]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[6]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[5]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[4]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[3]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[2]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[1]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_addr_i[0]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_sel_i[3]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_sel_i[2]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_sel_i[1]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0_sel_i[0]}]
set_driving_cell -lib_cell in01f80 [get_ports wb0_we_i]
set_driving_cell -lib_cell in01f80 [get_ports wb0_cyc_i]
set_driving_cell -lib_cell in01f80 [get_ports wb0_stb_i]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[31]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[30]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[29]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[28]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[27]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[26]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[25]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[24]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[23]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[22]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[21]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[20]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[19]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[18]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[17]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[16]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[15]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[14]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[13]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[12]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[11]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[10]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[9]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[8]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[7]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[6]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[5]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[4]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[3]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[2]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[1]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb0m_data_i[0]}]
set_driving_cell -lib_cell in01f80 [get_ports wb0_ack_i]
set_driving_cell -lib_cell in01f80 [get_ports wb0_err_i]
set_driving_cell -lib_cell in01f80 [get_ports wb0_rty_i]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[31]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[30]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[29]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[28]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[27]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[26]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[25]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[24]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[23]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[22]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[21]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[20]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[19]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[18]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[17]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[16]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[15]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[14]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[13]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[12]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[11]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[10]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[9]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[8]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[7]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[6]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[5]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[4]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[3]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[2]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[1]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1s_data_i[0]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[31]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[30]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[29]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[28]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[27]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[26]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[25]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[24]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[23]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[22]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[21]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[20]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[19]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[18]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[17]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[16]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[15]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[14]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[13]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[12]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[11]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[10]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[9]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[8]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[7]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[6]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[5]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[4]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[3]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[2]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[1]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_addr_i[0]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_sel_i[3]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_sel_i[2]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_sel_i[1]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1_sel_i[0]}]
set_driving_cell -lib_cell in01f80 [get_ports wb1_we_i]
set_driving_cell -lib_cell in01f80 [get_ports wb1_cyc_i]
set_driving_cell -lib_cell in01f80 [get_ports wb1_stb_i]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[31]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[30]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[29]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[28]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[27]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[26]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[25]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[24]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[23]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[22]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[21]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[20]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[19]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[18]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[17]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[16]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[15]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[14]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[13]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[12]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[11]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[10]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[9]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[8]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[7]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[6]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[5]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[4]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[3]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[2]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[1]}]
set_driving_cell -lib_cell in01f80 [get_ports {wb1m_data_i[0]}]
set_driving_cell -lib_cell in01f80 [get_ports wb1_ack_i]
set_driving_cell -lib_cell in01f80 [get_ports wb1_err_i]
set_driving_cell -lib_cell in01f80 [get_ports wb1_rty_i]
set_driving_cell -lib_cell in01f80 [get_ports {dma_req_i[0]}]
set_driving_cell -lib_cell in01f80 [get_ports {dma_nd_i[0]}]
set_driving_cell -lib_cell in01f80 [get_ports {dma_rest_i[0]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[31]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[30]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[29]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[28]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[27]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[26]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[25]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[24]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[23]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[22]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[21]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[20]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[19]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[18]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[17]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[16]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[15]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[14]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[13]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[12]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[11]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[10]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[9]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[8]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[7]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[6]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[5]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[4]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[3]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[2]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[1]}]
set_load -pin_load 1 [get_ports {wb0s_data_o[0]}]
set_load -pin_load 1 [get_ports wb0_ack_o]
set_load -pin_load 1 [get_ports wb0_err_o]
set_load -pin_load 1 [get_ports wb0_rty_o]
set_load -pin_load 1 [get_ports {wb0m_data_o[31]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[30]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[29]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[28]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[27]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[26]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[25]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[24]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[23]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[22]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[21]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[20]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[19]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[18]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[17]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[16]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[15]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[14]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[13]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[12]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[11]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[10]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[9]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[8]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[7]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[6]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[5]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[4]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[3]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[2]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[1]}]
set_load -pin_load 1 [get_ports {wb0m_data_o[0]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[31]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[30]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[29]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[28]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[27]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[26]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[25]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[24]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[23]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[22]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[21]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[20]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[19]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[18]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[17]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[16]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[15]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[14]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[13]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[12]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[11]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[10]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[9]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[8]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[7]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[6]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[5]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[4]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[3]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[2]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[1]}]
set_load -pin_load 1 [get_ports {wb0_addr_o[0]}]
set_load -pin_load 1 [get_ports {wb0_sel_o[3]}]
set_load -pin_load 1 [get_ports {wb0_sel_o[2]}]
set_load -pin_load 1 [get_ports {wb0_sel_o[1]}]
set_load -pin_load 1 [get_ports {wb0_sel_o[0]}]
set_load -pin_load 1 [get_ports wb0_we_o]
set_load -pin_load 1 [get_ports wb0_cyc_o]
set_load -pin_load 1 [get_ports wb0_stb_o]
set_load -pin_load 1 [get_ports {wb1s_data_o[31]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[30]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[29]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[28]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[27]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[26]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[25]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[24]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[23]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[22]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[21]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[20]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[19]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[18]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[17]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[16]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[15]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[14]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[13]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[12]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[11]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[10]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[9]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[8]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[7]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[6]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[5]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[4]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[3]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[2]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[1]}]
set_load -pin_load 1 [get_ports {wb1s_data_o[0]}]
set_load -pin_load 1 [get_ports wb1_ack_o]
set_load -pin_load 1 [get_ports wb1_err_o]
set_load -pin_load 1 [get_ports wb1_rty_o]
set_load -pin_load 1 [get_ports {wb1m_data_o[31]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[30]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[29]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[28]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[27]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[26]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[25]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[24]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[23]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[22]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[21]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[20]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[19]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[18]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[17]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[16]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[15]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[14]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[13]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[12]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[11]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[10]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[9]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[8]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[7]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[6]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[5]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[4]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[3]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[2]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[1]}]
set_load -pin_load 1 [get_ports {wb1m_data_o[0]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[31]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[30]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[29]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[28]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[27]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[26]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[25]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[24]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[23]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[22]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[21]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[20]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[19]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[18]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[17]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[16]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[15]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[14]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[13]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[12]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[11]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[10]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[9]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[8]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[7]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[6]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[5]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[4]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[3]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[2]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[1]}]
set_load -pin_load 1 [get_ports {wb1_addr_o[0]}]
set_load -pin_load 1 [get_ports {wb1_sel_o[3]}]
set_load -pin_load 1 [get_ports {wb1_sel_o[2]}]
set_load -pin_load 1 [get_ports {wb1_sel_o[1]}]
set_load -pin_load 1 [get_ports {wb1_sel_o[0]}]
set_load -pin_load 1 [get_ports wb1_we_o]
set_load -pin_load 1 [get_ports wb1_cyc_o]
set_load -pin_load 1 [get_ports wb1_stb_o]
set_load -pin_load 1 [get_ports {dma_ack_o[0]}]
set_load -pin_load 1 [get_ports inta_o]
set_load -pin_load 1 [get_ports intb_o]
create_clock [get_ports clk] -period 250 -waveform {0 125}
set_input_delay -clock clk 0 [get_ports rst_i]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[31]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[30]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[29]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[28]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[27]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[26]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[25]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[24]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[23]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[22]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[21]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[20]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[19]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[18]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[17]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[16]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[15]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[14]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[13]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[12]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[11]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[10]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[9]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[8]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[7]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[6]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[5]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[4]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[3]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[2]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[1]}]
set_input_delay -clock clk 0 [get_ports {wb0s_data_i[0]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[31]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[30]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[29]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[28]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[27]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[26]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[25]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[24]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[23]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[22]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[21]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[20]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[19]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[18]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[17]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[16]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[15]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[14]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[13]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[12]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[11]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[10]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[9]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[8]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[7]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[6]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[5]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[4]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[3]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[2]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[1]}]
set_input_delay -clock clk 0 [get_ports {wb0_addr_i[0]}]
set_input_delay -clock clk 0 [get_ports {wb0_sel_i[3]}]
set_input_delay -clock clk 0 [get_ports {wb0_sel_i[2]}]
set_input_delay -clock clk 0 [get_ports {wb0_sel_i[1]}]
set_input_delay -clock clk 0 [get_ports {wb0_sel_i[0]}]
set_input_delay -clock clk 0 [get_ports wb0_we_i]
set_input_delay -clock clk 0 [get_ports wb0_cyc_i]
set_input_delay -clock clk 0 [get_ports wb0_stb_i]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[31]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[30]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[29]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[28]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[27]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[26]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[25]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[24]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[23]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[22]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[21]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[20]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[19]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[18]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[17]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[16]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[15]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[14]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[13]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[12]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[11]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[10]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[9]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[8]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[7]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[6]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[5]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[4]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[3]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[2]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[1]}]
set_input_delay -clock clk 0 [get_ports {wb0m_data_i[0]}]
set_input_delay -clock clk 0 [get_ports wb0_ack_i]
set_input_delay -clock clk 0 [get_ports wb0_err_i]
set_input_delay -clock clk 0 [get_ports wb0_rty_i]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[31]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[30]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[29]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[28]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[27]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[26]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[25]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[24]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[23]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[22]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[21]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[20]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[19]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[18]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[17]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[16]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[15]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[14]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[13]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[12]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[11]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[10]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[9]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[8]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[7]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[6]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[5]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[4]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[3]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[2]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[1]}]
set_input_delay -clock clk 0 [get_ports {wb1s_data_i[0]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[31]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[30]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[29]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[28]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[27]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[26]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[25]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[24]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[23]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[22]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[21]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[20]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[19]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[18]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[17]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[16]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[15]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[14]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[13]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[12]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[11]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[10]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[9]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[8]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[7]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[6]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[5]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[4]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[3]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[2]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[1]}]
set_input_delay -clock clk 0 [get_ports {wb1_addr_i[0]}]
set_input_delay -clock clk 0 [get_ports {wb1_sel_i[3]}]
set_input_delay -clock clk 0 [get_ports {wb1_sel_i[2]}]
set_input_delay -clock clk 0 [get_ports {wb1_sel_i[1]}]
set_input_delay -clock clk 0 [get_ports {wb1_sel_i[0]}]
set_input_delay -clock clk 0 [get_ports wb1_we_i]
set_input_delay -clock clk 0 [get_ports wb1_cyc_i]
set_input_delay -clock clk 0 [get_ports wb1_stb_i]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[31]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[30]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[29]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[28]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[27]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[26]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[25]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[24]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[23]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[22]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[21]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[20]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[19]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[18]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[17]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[16]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[15]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[14]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[13]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[12]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[11]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[10]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[9]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[8]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[7]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[6]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[5]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[4]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[3]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[2]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[1]}]
set_input_delay -clock clk 0 [get_ports {wb1m_data_i[0]}]
set_input_delay -clock clk 0 [get_ports wb1_ack_i]
set_input_delay -clock clk 0 [get_ports wb1_err_i]
set_input_delay -clock clk 0 [get_ports wb1_rty_i]
set_input_delay -clock clk 0 [get_ports {dma_req_i[0]}]
set_input_delay -clock clk 0 [get_ports {dma_nd_i[0]}]
set_input_delay -clock clk 0 [get_ports {dma_rest_i[0]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[31]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[30]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[29]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[28]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[27]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[26]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[25]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[24]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[23]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[22]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[21]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[20]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[19]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[18]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[17]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[16]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[15]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[14]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[13]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[12]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[11]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[10]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[9]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[8]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[7]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[6]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[5]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[4]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[3]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[2]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[1]}]
set_output_delay -clock clk 0 [get_ports {wb0s_data_o[0]}]
set_output_delay -clock clk 0 [get_ports wb0_ack_o]
set_output_delay -clock clk 0 [get_ports wb0_err_o]
set_output_delay -clock clk 0 [get_ports wb0_rty_o]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[31]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[30]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[29]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[28]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[27]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[26]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[25]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[24]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[23]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[22]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[21]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[20]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[19]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[18]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[17]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[16]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[15]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[14]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[13]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[12]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[11]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[10]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[9]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[8]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[7]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[6]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[5]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[4]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[3]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[2]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[1]}]
set_output_delay -clock clk 0 [get_ports {wb0m_data_o[0]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[31]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[30]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[29]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[28]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[27]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[26]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[25]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[24]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[23]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[22]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[21]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[20]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[19]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[18]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[17]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[16]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[15]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[14]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[13]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[12]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[11]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[10]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[9]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[8]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[7]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[6]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[5]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[4]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[3]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[2]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[1]}]
set_output_delay -clock clk 0 [get_ports {wb0_addr_o[0]}]
set_output_delay -clock clk 0 [get_ports {wb0_sel_o[3]}]
set_output_delay -clock clk 0 [get_ports {wb0_sel_o[2]}]
set_output_delay -clock clk 0 [get_ports {wb0_sel_o[1]}]
set_output_delay -clock clk 0 [get_ports {wb0_sel_o[0]}]
set_output_delay -clock clk 0 [get_ports wb0_we_o]
set_output_delay -clock clk 0 [get_ports wb0_cyc_o]
set_output_delay -clock clk 0 [get_ports wb0_stb_o]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[31]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[30]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[29]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[28]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[27]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[26]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[25]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[24]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[23]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[22]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[21]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[20]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[19]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[18]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[17]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[16]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[15]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[14]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[13]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[12]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[11]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[10]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[9]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[8]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[7]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[6]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[5]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[4]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[3]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[2]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[1]}]
set_output_delay -clock clk 0 [get_ports {wb1s_data_o[0]}]
set_output_delay -clock clk 0 [get_ports wb1_ack_o]
set_output_delay -clock clk 0 [get_ports wb1_err_o]
set_output_delay -clock clk 0 [get_ports wb1_rty_o]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[31]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[30]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[29]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[28]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[27]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[26]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[25]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[24]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[23]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[22]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[21]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[20]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[19]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[18]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[17]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[16]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[15]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[14]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[13]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[12]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[11]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[10]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[9]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[8]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[7]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[6]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[5]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[4]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[3]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[2]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[1]}]
set_output_delay -clock clk 0 [get_ports {wb1m_data_o[0]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[31]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[30]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[29]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[28]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[27]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[26]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[25]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[24]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[23]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[22]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[21]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[20]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[19]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[18]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[17]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[16]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[15]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[14]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[13]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[12]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[11]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[10]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[9]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[8]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[7]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[6]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[5]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[4]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[3]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[2]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[1]}]
set_output_delay -clock clk 0 [get_ports {wb1_addr_o[0]}]
set_output_delay -clock clk 0 [get_ports {wb1_sel_o[3]}]
set_output_delay -clock clk 0 [get_ports {wb1_sel_o[2]}]
set_output_delay -clock clk 0 [get_ports {wb1_sel_o[1]}]
set_output_delay -clock clk 0 [get_ports {wb1_sel_o[0]}]
set_output_delay -clock clk 0 [get_ports wb1_we_o]
set_output_delay -clock clk 0 [get_ports wb1_cyc_o]
set_output_delay -clock clk 0 [get_ports wb1_stb_o]
set_output_delay -clock clk 0 [get_ports {dma_ack_o[0]}]
set_output_delay -clock clk 0 [get_ports inta_o]
set_output_delay -clock clk 0 [get_ports intb_o]
